3D NAND and 3D ReRAM

Time to wrap up this first pass at 3D NAND. There are a couple of points which I didn’t get to in the first two posts, which I’ll touch on here. Of particular interest is the relationship of 3D NAND to future post-NAND memory technologies, specifically ReRAM.

Conceptually in many respects, 3D NAND is closer to a post-NAND technology than it is to NAND as we know it today. The slide below from a 2009 Toshiba presentation tells the tale.

From the left, floating gate NAND rolls along to where the path splits with ever smaller NAND geometries  above and 3D NAND and other post-NAND technologies below. Other post-NAND include PCRAM, ReRAM, MRAM, etc.

What’s interesting is that 3D NAND is on the post-NAND branch and not on the NAND branch. Apparently this is because for 3D NAND the NAND string is perpendicular to the Silicon Substrate and other post-NAND technologies will depend on a similar three dimensionality.

Another slide from this same Toshiba presentation makes the point a different way.

In the center is the BiCS 3D Technology. Other technologies, including NAND and ReRam surround BiCS as potential extensions of BiCS 3D technology.

The point here is that BiCS technology can be applied to various memories to produce low cost data storage devices. When applied to NAND, the result is 3D BiCS-style NAND. When applied to ReRAM, the result will be 3D BiCS-style ReRAM and so forth.

BiCS is short for Bit-Cost Scalable technology. It is a 3D design strategy and as such allows greater capacity per footprint, which in turn results in lower bit cost. BiCS uses “a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layers to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material.”

Another Toshiba slide from this same presentation graphs the relation between capacity and bit cost. As one would expect, the more layers, the lower the cost. With BiCS, more layers and hence lower costs per bit can be achieved.

BiCS Flash appears to have the potential of a 10 Tbit/ chip.

At the bottom of the slide, Toshiba innocently wonders whether the market would be interested in such “huge” capacity?

Given cloud data center demands today, I doubt anyone is worrying about that one today- If the cost is right.

Toshiba has it right. Future trends will primarily be driven by cost per bit. The technology that will provide the most bits at the lowest cost will succeed.

Cost reduction is the most important issue.

For anyone interested in this Toshiba presentation, here is the link.

3D Resistive Random-Access Memory (RRAM)

RRAM and SanDisk/Toshiba’s 3D R/W technology deserves it’s own post, which hopefully I’ll get to in the not so distant future.

Suffice it to say, that it sure sounds like today SanDisk/Toshiba’s 3D R/W is RRAM.

Yoram apparently said as much at this year’s Flash Memory Summit:

“Further in the future, chip makers including SanDisk are developing 3-D structures that use changes in resistance to create denser chips. But the so-called resistive RAM will require EUV tools, he [Yoram Cedar] said.”

SanDisk has been looking for a new manager for its “3D ReRAM” team since August.

The interrelationship between BiCS 3D NAND and 3D RRAM bears watching.

Toshiba and SanDisk have licensed or otherwise invested in each other’s 3D technologies and today are co-developing both.

In 2008 SanDisk licensed it’s 3D R/W technology to Toshiba.

Then in Q1 2011, SanDisk “made an incremental strategic technology investment with Toshiba that covers a variety of technologies including a three-dimensional NAND architecture, known as Bit Cost Scalable or BiCS, which Toshiba had been developing independently.”

RRAM IP

Many companies have been working on RRAM, for a long time. A very, very long time- which in some respects is a good thing.

Most importantly, the patents on the basic RRAM switching concepts apparently have expired.

The slide below is from a Deepak C. Sekar presentation. Deepak is Chief Scientist at MonolithIC 3D Inc. He also spent almost three years at SanDisk working on both NAND and 3D crosspoint memory.

Deepak makes three points about RRAM IP in the slide above:

Patents, if any, on the basic switching concepts have expired.

Good patents on more advanced concepts exist (eg) Pt-replacement approaches, array architectures, doping, etc.

IP scenario for RRAM a key advantage. Other resistive memories have gate-keepers (eg) Basic patents on PCM, CB-RAM, STT-MRAM fro Ovonyx, Axon Technologies, Grandis. 

I suspect SanDisk and Toshiba have a particularly nice hand of good patents on the more advanced RRAM concepts, specifically array architectures.

The slide below is from SanDisk’s 2010 Investor Day.

Eli makes the point that  SanDisk holds “Fundamental patents in 3D diode arrays (apply to most 3D approaches)”

I’m going to end with this slide from the IMEC consortium. Its a nice summary showing floating gate NAND, 3D Vertical NAND, and RRAM graphed against Cost/Bit and chip capacity.

 

Here is the article where the slide above was taken. Apparently Toshiba/SanDisk hasn’t signed up for the collaborative effort.

“IMEC is working collaboratively with major memory manufacturers including Elpida, Hynix, Micron and Samsung on both flash and follow-on memory roadmaps

Toshiba [Sandisk] is a notable absentee from the program.”

There could be many reasons why Toshiba/SanDisk wouldn’t be interested in working with IMEC.

One would be that Toshiba/SanDisk feel they have the inside track on the roadmap.

About these ads

8 Responses to 3D NAND and 3D ReRAM

  1. MartyS says:

    Good summary Savo. I caught the new photos in your header. Nice.

    • savolainen says:

      Hey Marty,

      Yep it’s been time to update the header for a while now. My plan had been to add Yoram along with Sanjay and Judy. No need for that now

      Yoram will soon be gone. It will be interesting to see who takes over as CTO.

      I am guessing it will probably be Dan Inbar or Dr. Khandker Nazrul Quader. 

      Today Dan Inbar is GM OEM. This was the position that Yoram had before he became CTO in October 2010. As you probably know, Dan came to SanDisk in the FLSH acquisition. 

      Dan has also been giving presentations at analyst days. He can handle the spotlight.

      The only problem with Dan is that he appears to have a stronger background in business than engineering.

      If SanDisk wants technical engineering smarts then it might be Dr. Khandker Nazrul Quader.

      Today Khandker is senior vice president of memory technology, design. He has a doctorate in electrical engineering and has many patents. Khandker has been with SanDisk since 1995, even longer than Yoram and has been a speaker at the Flash Memory Summit.

      Regards,
      Savo

  2. MartyS says:

    Savo,
    I’ve been struggling to understand the differences between NAND used as an I/O accelerator and as a storage array and the various strategies (including Sandisk/Pliant’s) used for each. Any technical clarity would be much appreciated. Thanks.

    Marty

  3. MartyS says:

    Savo, sorry for cluttering your blog with comments, but the recent rumors of AAPL buying Anobit (you had the right target, wrong acquiror) and opening an Israeli semiconductor R&D facility scream out for your thoughts/comments.

    Marty

    • savolainen says:

      Hey Marty & Poofy,

      Apple’s pending acquisition of Anobit has many intriguing and relevant angles. As I see it, pretty much all neutral or positive for SanDisk.

      I agree with Oppenheimer’s comment that the move implicitly validates SanDisk.

      I’ll probably dedicate a post to the subject, but probably not until January.

      My next post will likely be on RRAM. With the holidays and all, I’m not sure I’ll get to that one this weekend.

      ****

      From what I’ve heard from an Israeli friend with Anobit-related sources, AAPL hopes to see this acquisition evolve along the same lines as its acquisition of P.A. Semi.

      Personally I’m not so sure about that vision.

      P.A. Semi had ARM expertise, which was way ahead of the curve for processor design.

      With the P.A. Semi acquisition, Apple was able to set itself up with cutting edge technological expertise in a processor technology which looks poised to become dominant in the next decade.

      Anobit look like smart folks, but their expertise is in controllers for planar NAND, a technology reaching the end of the line. With the acquisition Apple should be able to ride the status quo to the end of line or close.

      Apparently Apple has been using Anobit controllers. My guess is that Samsung is also a big Anobit customer.

      Safe to say Samsung can kiss that one goodbye.

      As far as X3 goes, Anobit talks a good line, but if they had the goods for 3 bits/cell, their customers would be shipping X3 in volume today.

      That they’re not, speaks volumes.

      Best,
      Savo

  4. Poofypuppy says:

    Hi Savo

    I’d be interested in your take on the Anobit acquisition by Apple as well. Specifically, what impact (if any) would Anobit have on SanDisk’s x3 semi-monopoly?

    “Analyst Jim Handy of Objective Analysis Semiconductor Market Research said that Anobit’s technology will be of growing importance to Apple as each generation of flash becomes more dense, more prone to errors and harder to correct. Anobit won the award for “Best of Show” at the 2010 Flash Memory Summit for its SSD controllers.

    According to Handy, Anobit technology will let Apple buy “raw NAND (the cheapest kind of NAND) at the lowest possible prices, preventing other companies from competing.”

    http://www.zdnet.com/blog/apple/another-driver-behind-apples-anobit-flash-controller-acquisition/11870

    Thanks,
    Poofypuppy

  5. MartyS says:

    “I’ll probably dedicate a post to the subject, but probably not until January.” Maybe you should charge subscription fees, Savo, and post weekly. LOL.

    So, are you saying that AAPL will need to do “something” further to obtain X3 & 3D expertise?

  6. more_ outside says:

    One thing still glossed over in these 3d presentations is that the area OUTSIDE the array grows in proportion to the number of layers, so the array area efficiency is quite poor. This would undo the cost advantage.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s

Follow

Get every new post delivered to your Inbox.

Join 29 other followers

%d bloggers like this: