Fab 5

March 21, 2010

Like it or not fab 5 is coming.

As Eli put it at Investor Day describing the need for new production capacity in the industry:

“You cannot grow from 10,000 petabytes [today’s industry capacity] to 60, or 70 or even 40,000 PB without new fabs. The question is not if, the question is when.”

For SanDisk and Toshiba this will mean a new fab 5.

Existing production space in fab 4 will be pretty much maxed out late 2010. Today SanDisk and Toshiba’s fab 3 + fab 4 deliver 35% of the world’s NAND output. To hold their own, fab 5 is a necessity for both SanDisk and Toshiba.

As is usually the case, the devil- and the promise- is in the details. This post is a first pass at what fab 5 means.


Fab 5 will be a mega-fab. It will be a beast. The slide below is from this year’s Investor Day.

Fab 5 will be expensive at $8 billion ± . For perspective that’s about $3 billion more than aircraft carrier.

At full capacity fab 5 will be able to produce 200,000 300 mm wafers/month.

It will need to support EUV and it will need to be able to adapt to post-NAND technologies.

From SanDisk’s perspective the post-NAND technology will be (hopefully) SanDisk’s 3D R/W which was discussed in my last post.

SanDisk expects that this transition to post-NAND will be more complex than the transition from SLC to MLC which took 3 years- 2002- 2005. Fab 5 will be expected to accommodate both NAND and post-NAND designs- at the same time- for an extended period.

Why a mega-fab and not something smaller?

According to Eli, its all about economies of scale. From Investors Day:

“Eli: You have to build a mega-fab because otherwise you are not going to make much difference. [laughs] First of all, but more importantly, you are not going to be competitive.

Small fabs don’t cut it. OK, its really a mega-fab or stay at home.

That’s the magnitude. But that by itself has an implication on when, because if you could do it in tiny little increments, or something [you can’t do it in small pieces]. Now I would say that those mega-fabs don’t necessarily ramp overnight. This is not like a 6 month exercise.

A mega-fab could easily take two to three years to ramp- and the investments would be spread accordingly.”

Industry Supply

The slide below from this year’s Investor Day is not only provocative, but instructive.

Heretofore, on seeing this slide, I have been focussed on the markets for flash and their hockey-stick ramp- year by year. This time around- the left hand scale: millions of gigabytes (GB)- jumped out at me.

1,000,000 GBs= 1 petabyte (PB) = 1000 terabytes (TB).

PB is often used in describing annual capacity of the flash industry. Today’s supply and demand is typically pegged at about 10 to 11,000 PB. Looking at the slide, sure enough- 10 to 11,000± PB for early 2010.

The graph, based on data from Gartner, shows supply and demand growing to 75,000± PB by 2013.

Wishful thinking.

To my mind, supply is going to come up far short.

Eli ran through the basic math in response to a question at Investor Day (included below). Today’s 10 to 11,000± PB will likely be able to grow to 30,000 PB in existing fabs primarily on the strength of shrinks to 1x.

It will take an additional 7+ new mega-fabs- fully ramped and running at full capacity to add another 45,000 PB by 2013.

My guess is that the equivalent of only three new mega-fabs will be up and running by that date. Fab 5 (meg-fab) for Sandisk/Toshiba. A mega-fab for Samsung. A regular fab (Singapore) for Intel/Micron. And an equivalent regular fab for Hynix.

I just don’t see how these four players will be able to fund, build, and fully ramp more by 2013.

Not in this uncertain economic environment. Not with the looming technological uncertainties. Not with both of the big guys- Samsung and Toshiba/SanDisk currently preaching caution.

And not with the cost, complexity and time required for each new fab.

Just for kicks I went back and looked at the timeline for Fab 4 (a mega-fab).  Fab 4 was announced mid 2006. Construction started that same year. The building was finished a year later, in early fall 2007. Mass production began at the end of 2007. By the end of 2008 production had ramped to about half of full capacity. By the end of 2010+, Fab 4 will be at full capacity.

Total time for Fab 4 from announcement to full ramp= 4.5 years+. Unless SanDisk/Toshiba want to be working on two fabs at once, I don’t see how we’ll see more than Fab 5 by 2013. Heck and it hasn’t even been announced yet.

Other players are in the same boat.

If only the equivalent of 3 new mega-fabs are built, and the shrinks to 1x go as planned, it seems to me that by 2013, industry capacity will be far below the 75,000± PB shown in the Gartner slide above. 50,000± PB (max) looks more like it.

What this will mean is anyone’s guess. Likely some markets won’t experience the growth they otherwise would be able to.

In any case, those controlling supply would seem to be in the driver’s seat- demand willing.

Here is Eli’s math from Investor Day:

“Q: OK very good. And how many new fabs would need to be built then to reach your estimated demand in the out years [2013]? At one point a few years back you were talking about 6 new fabs.

Eli: OK, and don’t hold me to it. To do that math.

Lets say that 1x generation product is between lets say 2.5 and 3 TB per wafer, approximately that- lets say 3 TB per wafer. You have to be really really good to get 3 TB per wafer, and probably use 2 to 3 bits per cell.

That means 30,000 PB in 2013, an incremental 30,000 PB would require another 10 million wafers which is 5 mega-fabs, assuming 1x @ pretty good yields @ 3 bits per cell.

This is the point I was making earlier- that the projected growth in demand requires very substantial new capacity.

The existing capacity is already generating 10,000 PBs- 11,000. So lets say it can go to 30,000 PB. If you want to build another 30,000 you need to have another 5 or so fabs- mega-fabs.

Q: On an average of $8B per fab?

Eli: Roughly.

Q: Roughly, plus maintenance capex. That’s a big investment- a big risk.

Eli: Yes. Somebody told me that a nuclear aircraft carrier cost about $5B. That gives you an idea how big $8 billion is, but as I said, it’s spread over a three year period- investment wise. In any kind of new capacity it would be very likely with Toshiba so our number would be less than that number.

Q: I hope so.

Eli: Me too. [laughter]”

Previous Fab 5 Investment Model

Fab 5 has been a glimmer in SanDisk/ Toshiba’s eye for years now- at least since 2006. In early 2008, financing details were discussed at SanDisk’s Investor Day.

At least back then, SanDisk looked to have a lot of flexibility. The slide below is from Investor Day 2008.

As far as capital investment, Toshiba was willing to assume 75% of the deal. SanDisk would only have to cough up 25%. Sweetening the deal, SanDisk had the option to convert to 50% / 50%.

Capacity was to have been divided 50%/ 50% whereby SanDisk would receive 25% of captive capacity and 25% cost-plus committed foundry. SanDisk had the option to convert committed foundry to captive or to non-committed foundry.

Where things stand now is anyone’s guess. No one is talking. Last month Toshiba even released a press release to the effect that no decisions have been made for Fab 5. Eli has been doing his part in playing down the possibility of Fab 5- which is what the analysts have wanted to hear.

All that said, fab 5 is not a matter of if, but when. And when is getting closer.

My guess is that fab 5 will be announced this year. The cost will be closer to $9 billion once the dust clears. The location will be in Iwate in western Japan. The ramp will be similar to fab 4.

The building itself will be dedicated in 2011 and sometime in 2012 capacity will have ramped to about half of full capacity. EUV equipment will continue to be an issue. 3D R/W will be up and running by 2013, but only in small volumes.

My guess is that the fab 5 investment model from 2008 is still relevant.

SanDisk will at least hold its current market share, and total industry capacity will be closer to 40,000 PB than Gartner’s 75,000 PB by 2013 with demand exceeding supply.

Lots of guesses. In any case, the next few years should be interesting with plenty of twists and turns.

SanDisk and Toshiba have a lot riding on fab 5 and 3D R/W.

SanDisk’s 3D Read/Write

March 7, 2010

What a difference a year makes.

12 months ago, SanDisk was crashing and burning. Investor Day 2009 never took place. As Eli put it- it would have been like standing on the podium, as a Man-on-Fire, talking about how negative things looked.

The image below comes to mind.

Well that is then and this is now.

This year it was smiles all around. Even Judy delivered- with upped guidance for Q1- minutes after the market closed. Very clever too- to hold back on updating the full year til the Q1 conference call.

Keep ‘em guessing on how much up- up will be for 2010. Lots of headroom here.

SanDisk has the 5+ hour replay of Investor Day up for the listening. For any serious investor, this is great stuff. Carefully organized and served up on silver platter. Not to be missed.

As a follow-on to Investor Day, SanDisk participated in Morgan Stanley’s Tech Conference (MS) this last week- also available as a replay. Following close on the heels of Investor Day, it turned out to be an addendum of sorts with additional detail.

My plan is to work my way through this material carefully, over the next few months- as time allows- topic, by topic.

Today’s topic is SanDisk’s 3D Read/Write (R/W)- a huge looming story.

Heretofore SanDisk has been tight lipped. Those days now appear over. More info about 3D R/W was served up at this Investor’s Day and MS, than the previous 5 years of investor days, conference calls and conferences combined.

Why this change of heart- now?

I can think of several possible reasons- confidence that the technology is commercially viable; confidence that the core IP is secured; gamesmanship with competitors; and the calculated decision to start educating the investment community- before any fab 5 announcements.

Before getting into new stuff, a bit of background is probably in order.


SanDisk comes by its 3D chip technology through its acquisition of Matrix Semiconductor back in 2005. Probably $250 million very wisely spent.

Matrix itself was founded in 1998 by Thomas Lee of AMD/ Rambus;  Mark Johnson of AMD/ Rambus/ MIPS/ Transmeta and Mike Farmwald, founder of Chromatic Research (and a co-founder of Rambus). Good bloodlines.

Matrix’s engineers adapted the normal manufacturing processes used for LCD screens to memory chips. They figured out how to layer polycrystalline silicon on top of a base chip and then re-crystallize it to form active 3D matrices.

Matrix’s 3D chip technology was something entirely different from NAND.  It was not a variation of floating gate or charge trapping, but something referred to as antifuse.

Instead of storing electrical charges, the chip had gazillions of microscopic fuses. When info was read to such a chip, fuses were either blown or left alone, storing the info permanently (up to 100 years.)

Chips worked as advertised and shipped commercially.

So far so good, but the not-so minor problem was that this technology was only one-time programable (OTP). It stores data just fine, but only once. The chip was not re-programable.

The challenge Sandisk took up was to turn this OTP technology into read-write (R/W). Apparently great progress has been made.

Looking over the patent parade, SanDisk appears to have solved the R/W problem by setting resistance within the fuses- instead of just burning them away.

This breakthrough is accomplished by doping the semiconductor material forming the fuses.  It even looks like it is possible to store multiple resistance states in the same memory cell- but no one is talking publicly about that.

Today SanDisk refers to its 3D (R/W) technology as scalable cross point diode arrays. SanDisk feels “3D R/W is the most likely successor for NAND in the coming decade.”

Memory Technologies’ Cost Curves

In this year’s Investor Day, Eli used the slide below to illustrate the potential story through 2016 and how various technologies might stack up in terms of cost per bit as far as their ability to disrupt NAND.

NAND as we know it, is slowing down as the technology runs up against physical limits. This is shown by the red NAND line flattening out in the black dotted section.

The slide shows the end of the road for NAND in 2014. This is likely just sloppy graphics. Eli made the point that (2D) NAND will likely be with us through 2020- though at the end likely serving legacy markets.

(SNDK) 3D is shown as starting up in 2013 in the optimistic scenario and 2014 in the conservative scenario. This same slide was shown in 2008 with 3D starting in 2012.

What happened?

My guess is that fab 5 and 3D are tied together and when fab 5 was postponed, commercial 3D was too.

This slide also shows that Ferroelectric RAM, MRAM, and Phase Change Memory (PCM) don’t look competitive.

BICS is another matter. The optimistic BICS line and optimistic 3D line are shown one over the other.

When this same slide was shown in 2008, BICS was nowhere to be seen.


BICS is vertical NAND, being developed by Toshiba and also a variant is being developed by Samsung.

Toshiba calls its 3D NAND implementation: P-BiCS (Pipe-shaped Bit Cost Scalable) and in 2009 had a 16-layer, 32Gbit prototype chip, built using 60nm process technology.

3D BICS MLC is apparently enabled by the U-shaped cell string. According to press: only “One more breakthrough is required in the processes of stacking cells and opening the through-hole to lower the cost.”

This said, Toshiba had this technology back in 2008 when Toshiba decided to sign on with SanDisk to jointly develop SanDisk’s 3D cross point diode arrays. Toshiba also agreed to make licensing payments to SanDisk for the privilege.

The problem that BICS faces is the same problem that 2D NAND is facing: a declining numbers of electrons. SanDisk’s 3D resistive memory doesn’t depend on how many electrons are left.

On the other hand, BICS would seem to remain within the confines of the semiconductor industry maxim, being “change as little as possible”- a proven recipe for success.

BICS is one to watch.

SanDisk’s 3D (Read/Write) Memory- Scalable Cross-point Diode Array

At Investor’s Day Eli, commenting on this slide, noted that a 3D R/W chip with 8 layers of stacked cross-point diode arrays, which is equivalent to 8 bits per cell or 8x, is going to be feasible.

Eli also said that development is now proceeding at Yokkaichi, which likely means Fab 4.

This is new news. Then at MS, Eli elaborated that “it’s [3D] not in production. It’s not in pilot production. It’s in intensive R&D mode- very intensive.”

Fighting words.

At Investor Day Eli went on to point out that SNDK 3D R/W, if successful, would trigger the second wave for SSDs:

“Now, if we are successful with 3D R/W, and by all means I say if, because until we do it, we haven’t done it. If we can succeed in that then 3D R/W would with the projected cost structure, will definitely give a second wave on the SSD.

Basically it has the economic [pause] you can kind of see it, if you take either the 3D optimistic or conservative, you can see that the cost, this is an exponential cost curve, is substantially lower than what can be done with NAND, and we also believe that issues like endurance will be far less, frankly, will not be an issue.”

Eli’s comment regarding endurance should be noted. BICS as a NAND variant would likely have the same endurance issues as 2D NAND.

If SanDisk 3D doesn’t have endurance issues and has best cost structure, then SNDK 3D SSDs (cross-point diode array technology) would look poised to displace hard disk drives across the board.

NAND and Post-NAND Fabs in the Coming Decade

Some of Eli’s comments on this slide from Investor Day on existing NAND fabs:

“ So what about this post-NAND? What’s going to happen to all those fabs? The existing NAND meg-fab is a very large fab- 200,000 wafer’s/month, 300mm. Will go to 1x nm.

By 2012/13, they will be highly depreciated. They will be highly cost effective. They will generate, I believe, very attractive margins for a long period of time. They will be throwing off a long tail, a long fat tail of cash, I believe, and very likely to the end of the decade.

And the reason for that is, because at 1x, you have such a good cost structure, particularly when you are depreciated. You can do 128Gbit chip and with that- 16GB on a chip- and with that you can cover a very very large train [??] of legacy products that are growing- the markets are growing.

So I think that these investments are going to have a second life, in fact benefit, from the fact that there is a slowdown in NAND and therefore there is far less need to continue to invest- to upgrade them. So basically you get to a certain point, you cannot go any further with immersion lithography, you are down at the edge. No one can do any better. And basically you have the market for that.”

In other words, for SanDisk/Toshiba Fabs 3 and 4 are going to end up as 1x NAND fabs based on immersion lithography. Eli took that thought and expanded it at MS:

“Eli Harari: Our assumption is that our existing captive supply for NAND will be gainfully employed at down to the 1x nanometer node for a long time to come and it would make very little sense for us to tear it up so we could get the clean room space to put any special equipment that’s required.

In the case and we’re talking about for 3D, the timing for 3D is such that we’re talking about really the advent of EUV lithography and that would require its own manufacturing space. It just makes no sense to take a very highly productive, highly depreciated NAND fab and stop it to three out of four [implies 75% of its life]. So 3D manufacturing would entail its own dedicated production.

Atif Malik: On that subject, there is quite a bit of debate about the timing of EUV the readiness of EUV. So I just want to get your thoughts on – we definitely need EUV at 11xnm or can we live with multiple patterning, triple or quadruple patterning to get it lower on its shrink path.

Eli: Right. So Intel has talked about going all the way to 11 nm with immersion scanners- through exposing a layer 5 times. You can do this when you only need to define one layer. For logic, for microprocessors, that may be possible- even though rather expensive.

But realistically for flash memory, NAND flash, or 3D, one of the most attractive features of EUV is that it takes you away from the need for multiple exposures. You don’t need to do dual exposure, double exposure, or 5x exposure- 5 times exposure.

Its single exposure, so even though the equipment may be more costly the throughput and productivity is better.

Now one of the things for us that 3D offers is at least in theory if we can make it work at 2x, technology node, we think that it should be much more readily scalable to 11 nm or whatever the lithography will allow us to do and therefore it will benefit to a greater degree from EUV than other technologies.”

Eli packed a lot into those brief comments. It appears that the plan is to produce commercial 3D at fab 5 at 1x using EUV. First 3D efforts will likely target 2x- probably in pilot production. Implied is that these efforts will be based on immersion lithography and likely in fab 4 when SanDisk/Toshiba gets to that node.

This post has gone on long enough, so I’m going to stop here.

Lots of ifs here with 3D. Lots of promise too.


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