SanDisk’s 3D Read/Write

What a difference a year makes.

12 months ago, SanDisk was crashing and burning. Investor Day 2009 never took place. As Eli put it- it would have been like standing on the podium, as a Man-on-Fire, talking about how negative things looked.

The image below comes to mind.

Well that is then and this is now.

This year it was smiles all around. Even Judy delivered- with upped guidance for Q1- minutes after the market closed. Very clever too- to hold back on updating the full year til the Q1 conference call.

Keep ‘em guessing on how much up- up will be for 2010. Lots of headroom here.

SanDisk has the 5+ hour replay of Investor Day up for the listening. For any serious investor, this is great stuff. Carefully organized and served up on silver platter. Not to be missed.

As a follow-on to Investor Day, SanDisk participated in Morgan Stanley’s Tech Conference (MS) this last week- also available as a replay. Following close on the heels of Investor Day, it turned out to be an addendum of sorts with additional detail.

My plan is to work my way through this material carefully, over the next few months- as time allows- topic, by topic.

Today’s topic is SanDisk’s 3D Read/Write (R/W)- a huge looming story.

Heretofore SanDisk has been tight lipped. Those days now appear over. More info about 3D R/W was served up at this Investor’s Day and MS, than the previous 5 years of investor days, conference calls and conferences combined.

Why this change of heart- now?

I can think of several possible reasons- confidence that the technology is commercially viable; confidence that the core IP is secured; gamesmanship with competitors; and the calculated decision to start educating the investment community- before any fab 5 announcements.

Before getting into new stuff, a bit of background is probably in order.


SanDisk comes by its 3D chip technology through its acquisition of Matrix Semiconductor back in 2005. Probably $250 million very wisely spent.

Matrix itself was founded in 1998 by Thomas Lee of AMD/ Rambus;  Mark Johnson of AMD/ Rambus/ MIPS/ Transmeta and Mike Farmwald, founder of Chromatic Research (and a co-founder of Rambus). Good bloodlines.

Matrix’s engineers adapted the normal manufacturing processes used for LCD screens to memory chips. They figured out how to layer polycrystalline silicon on top of a base chip and then re-crystallize it to form active 3D matrices.

Matrix’s 3D chip technology was something entirely different from NAND.  It was not a variation of floating gate or charge trapping, but something referred to as antifuse.

Instead of storing electrical charges, the chip had gazillions of microscopic fuses. When info was read to such a chip, fuses were either blown or left alone, storing the info permanently (up to 100 years.)

Chips worked as advertised and shipped commercially.

So far so good, but the not-so minor problem was that this technology was only one-time programable (OTP). It stores data just fine, but only once. The chip was not re-programable.

The challenge Sandisk took up was to turn this OTP technology into read-write (R/W). Apparently great progress has been made.

Looking over the patent parade, SanDisk appears to have solved the R/W problem by setting resistance within the fuses- instead of just burning them away.

This breakthrough is accomplished by doping the semiconductor material forming the fuses.  It even looks like it is possible to store multiple resistance states in the same memory cell- but no one is talking publicly about that.

Today SanDisk refers to its 3D (R/W) technology as scalable cross point diode arrays. SanDisk feels “3D R/W is the most likely successor for NAND in the coming decade.”

Memory Technologies’ Cost Curves

In this year’s Investor Day, Eli used the slide below to illustrate the potential story through 2016 and how various technologies might stack up in terms of cost per bit as far as their ability to disrupt NAND.

NAND as we know it, is slowing down as the technology runs up against physical limits. This is shown by the red NAND line flattening out in the black dotted section.

The slide shows the end of the road for NAND in 2014. This is likely just sloppy graphics. Eli made the point that (2D) NAND will likely be with us through 2020- though at the end likely serving legacy markets.

(SNDK) 3D is shown as starting up in 2013 in the optimistic scenario and 2014 in the conservative scenario. This same slide was shown in 2008 with 3D starting in 2012.

What happened?

My guess is that fab 5 and 3D are tied together and when fab 5 was postponed, commercial 3D was too.

This slide also shows that Ferroelectric RAM, MRAM, and Phase Change Memory (PCM) don’t look competitive.

BICS is another matter. The optimistic BICS line and optimistic 3D line are shown one over the other.

When this same slide was shown in 2008, BICS was nowhere to be seen.


BICS is vertical NAND, being developed by Toshiba and also a variant is being developed by Samsung.

Toshiba calls its 3D NAND implementation: P-BiCS (Pipe-shaped Bit Cost Scalable) and in 2009 had a 16-layer, 32Gbit prototype chip, built using 60nm process technology.

3D BICS MLC is apparently enabled by the U-shaped cell string. According to press: only “One more breakthrough is required in the processes of stacking cells and opening the through-hole to lower the cost.”

This said, Toshiba had this technology back in 2008 when Toshiba decided to sign on with SanDisk to jointly develop SanDisk’s 3D cross point diode arrays. Toshiba also agreed to make licensing payments to SanDisk for the privilege.

The problem that BICS faces is the same problem that 2D NAND is facing: a declining numbers of electrons. SanDisk’s 3D resistive memory doesn’t depend on how many electrons are left.

On the other hand, BICS would seem to remain within the confines of the semiconductor industry maxim, being “change as little as possible”- a proven recipe for success.

BICS is one to watch.

SanDisk’s 3D (Read/Write) Memory- Scalable Cross-point Diode Array

At Investor’s Day Eli, commenting on this slide, noted that a 3D R/W chip with 8 layers of stacked cross-point diode arrays, which is equivalent to 8 bits per cell or 8x, is going to be feasible.

Eli also said that development is now proceeding at Yokkaichi, which likely means Fab 4.

This is new news. Then at MS, Eli elaborated that “it’s [3D] not in production. It’s not in pilot production. It’s in intensive R&D mode- very intensive.”

Fighting words.

At Investor Day Eli went on to point out that SNDK 3D R/W, if successful, would trigger the second wave for SSDs:

“Now, if we are successful with 3D R/W, and by all means I say if, because until we do it, we haven’t done it. If we can succeed in that then 3D R/W would with the projected cost structure, will definitely give a second wave on the SSD.

Basically it has the economic [pause] you can kind of see it, if you take either the 3D optimistic or conservative, you can see that the cost, this is an exponential cost curve, is substantially lower than what can be done with NAND, and we also believe that issues like endurance will be far less, frankly, will not be an issue.”

Eli’s comment regarding endurance should be noted. BICS as a NAND variant would likely have the same endurance issues as 2D NAND.

If SanDisk 3D doesn’t have endurance issues and has best cost structure, then SNDK 3D SSDs (cross-point diode array technology) would look poised to displace hard disk drives across the board.

NAND and Post-NAND Fabs in the Coming Decade

Some of Eli’s comments on this slide from Investor Day on existing NAND fabs:

“ So what about this post-NAND? What’s going to happen to all those fabs? The existing NAND meg-fab is a very large fab- 200,000 wafer’s/month, 300mm. Will go to 1x nm.

By 2012/13, they will be highly depreciated. They will be highly cost effective. They will generate, I believe, very attractive margins for a long period of time. They will be throwing off a long tail, a long fat tail of cash, I believe, and very likely to the end of the decade.

And the reason for that is, because at 1x, you have such a good cost structure, particularly when you are depreciated. You can do 128Gbit chip and with that- 16GB on a chip- and with that you can cover a very very large train [??] of legacy products that are growing- the markets are growing.

So I think that these investments are going to have a second life, in fact benefit, from the fact that there is a slowdown in NAND and therefore there is far less need to continue to invest- to upgrade them. So basically you get to a certain point, you cannot go any further with immersion lithography, you are down at the edge. No one can do any better. And basically you have the market for that.”

In other words, for SanDisk/Toshiba Fabs 3 and 4 are going to end up as 1x NAND fabs based on immersion lithography. Eli took that thought and expanded it at MS:

“Eli Harari: Our assumption is that our existing captive supply for NAND will be gainfully employed at down to the 1x nanometer node for a long time to come and it would make very little sense for us to tear it up so we could get the clean room space to put any special equipment that’s required.

In the case and we’re talking about for 3D, the timing for 3D is such that we’re talking about really the advent of EUV lithography and that would require its own manufacturing space. It just makes no sense to take a very highly productive, highly depreciated NAND fab and stop it to three out of four [implies 75% of its life]. So 3D manufacturing would entail its own dedicated production.

Atif Malik: On that subject, there is quite a bit of debate about the timing of EUV the readiness of EUV. So I just want to get your thoughts on – we definitely need EUV at 11xnm or can we live with multiple patterning, triple or quadruple patterning to get it lower on its shrink path.

Eli: Right. So Intel has talked about going all the way to 11 nm with immersion scanners- through exposing a layer 5 times. You can do this when you only need to define one layer. For logic, for microprocessors, that may be possible- even though rather expensive.

But realistically for flash memory, NAND flash, or 3D, one of the most attractive features of EUV is that it takes you away from the need for multiple exposures. You don’t need to do dual exposure, double exposure, or 5x exposure- 5 times exposure.

Its single exposure, so even though the equipment may be more costly the throughput and productivity is better.

Now one of the things for us that 3D offers is at least in theory if we can make it work at 2x, technology node, we think that it should be much more readily scalable to 11 nm or whatever the lithography will allow us to do and therefore it will benefit to a greater degree from EUV than other technologies.”

Eli packed a lot into those brief comments. It appears that the plan is to produce commercial 3D at fab 5 at 1x using EUV. First 3D efforts will likely target 2x- probably in pilot production. Implied is that these efforts will be based on immersion lithography and likely in fab 4 when SanDisk/Toshiba gets to that node.

This post has gone on long enough, so I’m going to stop here.

Lots of ifs here with 3D. Lots of promise too.


30 Responses to SanDisk’s 3D Read/Write

  1. Chingadera says:

    Savo, Good morning. I have been out with pneumonia. I think that Sandisk is much closer to viable 3d than they are showing. I think once again, a major sandbag. Thanks. Chinga

    • savolainen says:

      Greetings Chinga,

      Hope you are feeling better.

      A little while ago, I asked about what sort of overlap there might be for equipment needed for NAND and 3D R/W. As you are probably aware, Eli addressed this at MS & Investor Day- at least in general terms.

      There appears to be a lot of overlap and 3D node-wise is limited by whatever the lithography will allow.

      3D R/W can be fabricated using immersion scanners- which is state of the art for NAND today. Then when EUV arrives- EUV will likely be the name of the game- because it will be faster and this means a lot when there are lots of layers. Each layer will need to be scanned and with 3D R/W as currently discussed @ 8 layers that would mean 8 exposures- with EUV.

      Eli discussed Intel’s approach (microprocessors) of using immersion scanners down to 11nm by using multiple exposures- up to 5 exposures- for one layer. If one were to use this on an 8-layered chip like 3D, one would have 40 exposures per chip- hence EUV, although more expensive, probably makes sense if each layer would only need one exposure- a total of 8 for an 8 layer chip.

      Eli was saying that even though EUV equipment will be more costly- the throughput and productivity is better when all is accounted for.

      For 3D, fabs will be much more lithography and etch than furnaces.

      I am also guessing that 8 layers would be only the beginning- if SNDK can get this baby into production.


      • bob77977 says:

        hi savo,
        can you please explain why production of 8 separate layers of 3D comes out cheaper
        than production of 8 NAND chips.

  2. MorganBucks says:

    Sandisk 3D LLC Reveals Method to Make and Program Carbon Nanotube Fabric Memory Cells and Steering Elements

    Sandisk 3D LLC (Milpitas, CA) earned U.S. Patent 7,667,999 for its method to form a rewriteable nonvolatile memory comprised of a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels.

    Carbon nanotube memories are believed to operate by flexing of individual carbon nanotubes or carbon nanotube ribbons in an electric field. This flexing mechanism requires space within which the carbon nanotubes can flex. In nanotechnologies, forming and maintaining such an empty space is extremely difficult.

    The Sandisk 3D method is used to form a memory array in which memory cells are comprised of carbon nanotube fabric and a steering element, such as a diode or a transistor, arranged electrically in series.

    Sandisk 3D inventors S. Brad Herner and Roy E. Scheuerlein also developed a method for programming a carbon nanotube memory cell, in which the memory cell includes a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor. Also the entire carbon nanotube memory cell is formed above a substrate and the carbon nanotube fabric has a first resistivity. The programming method includes: applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity is less than the first resistivity.

    • savolainen says:

      Greetings MorganBucks,

      I haven’t looked over that patent, but my suspicion it that it would have to do with the 3D technology that might follow SNDK’s scalable cross point diode arrays. Sometime in the distant future- post 2020++.

      Never too early to start patenting though, even stuff at the edge of the edge- like how nanotubes might be used in memory applications.

      As I understand it, nanotubes are really difficult to make, and especially so in the large quantities needed for commercial applications.

      One of the really important topics I didn’t get to in this SNDK 3D post was IP. If scalable cross point diode arrays turn out to be the next great thing, SNDK is sitting really pretty- thanks to the Matrix acquisition.

      When SNDK acquired Matrix, it also acquired the 100+ Matrix 3D diode array patents, which may extend beyond just the diode array approach.

      As you are probably aware, the latest Samsung royalty agreement specifically excludes 3D.

      SNDK’s diode array patents are likely far stronger and far reaching than its MLC patents. I would venture to guess, they could control the industry, if this is the way things go.


  3. Poofypuppy says:

    Good stuff, thanks Savo.

  4. sndk_long says:

    Housekeeping question, Savo: did you do the MS transcript yourself, or did you find it online somewhere? I’ve tried to find a copy somewhere, but haven’t found one (at least not a free one), and for some reason the webcast link on Sandisk’s site hasn’t worked for me.


    • savolainen says:

      Hey sndk_long,

      I transcribed the portions of MS included here. If I end up transcribing it all, I will post it- though I doubt this will happen soon.

      This MS was really good. It kind of served as a second Q&A to Investor Day. My tentative plan is to do a post on fab 5 next. As Eli put it re fab 5 – its not a question of if, but when.


  5. AndyW says:

    Nice summary of 3D. I don’t think SanDisk has anything to worry about from BiCS. The problem with BiCS (which is never mentioned by Toshiba) is the quickly vanishing string currents as density increases (through string lengthening). BiCS and Samsung’s VRAT and TCAT equivalent approaches have non-crystalline channels making even short strings have small worst case string currents. I actually have experimental data that will be published soon in the IEEE showing how the string currents in such approaches quickly vanish. The usual way to sustain the string current as length increases is to overdrive the other cell gates during read but this severely affects disturbs.

    • savolainen says:

      Hey Andy,

      Thanks for your comments on the problems with BiCs. I will try to keep an eye out for your IEEE article. If you think of it, and are so inclined, post a link here. It would be much appreciated.

      How would you handicap SanDisk’s chances at a commercially viable 3D R/W technology- in production- say by 2014?


  6. MorganBucks says:

    Latest Eli quote on 3D:
    Do hard drives possess a bright future with the ever expanding size of smaller form factors?

    No. We are developing 3D memory which is nothing but small diodes stacked like skyscraper in a nano form.
    These can scale up over time to large amounts of memory sizes upto 1 tera byte or more. We plan to launch these by 2014 if research on them is successful. They have a possibility to disrupt the market. Going forward we see hard drives being limited to only servers. The desktop PC market is already on a stagnancy globally. Emerging markets like India are going to bypass the desktops completely and adopt the mobile PCs (notebooks) directly. The solid state drives are also going to give tough competition to hard drives.

    • savolainen says:

      Hey MorganBucks,

      That Eli quote from Economic Times (India) is really interesting. Tho something could have been lost in translation. Confirming comments would be nice.

      In any case, Eli says that terabyte in a chip seems feasible. Putting this together with what we know from Investor Day and Morgan Stanley etc. Eli is all but saying that the 3D vision is to go far beyond the eight layers discussed so far- “like a skyscraper in nano form.”

      At the 1x node 128 Gb (2D) chips have been discussed. Converting to GB- 16 GB.

      If each layer of 3D at 1x had 16GB, it would take 62 layers to get to 1000 GB or a terabyte (TB). Even if 32 GB chip were to be feasible as a layer- and I’ve never heard it mentioned- that would still be 32 layers.

      Either 64 or 32 would qualify as a nano skyscraper. Certainly a story to watch.

      I suspect that when Eli starts talking about how 3D will re-energize Moore’s law he is thinking primarily up rather than smaller. At least til we get to nanotubes- 😉


  7. flip says:

    What is the contingency if there is still no EUV for 1x nm? It is quite possible since we have Toshiba/Sandisk already doing 24 nm and the next step would be 1x nm in the next several years. EUV is not going to be ready then, probably not until ~2020.

    • savolainen says:

      Hey flip,

      That’s another good question for an analyst to ask Eli directly- again. As I recall, at either Investor Day or MS, the question was asked and Eli sidestepped adroitly.

      I suspect that if pinned down, Eli would say that its likely EUV is going to be viable before ~2020- but no promises.

      As I understand it, progress is being made in EUV, but its not ready for prime time yet. According to Electronics Weekly:

      “ASML is currently building six pre-production EUV machines for delivery in the 2010 to 2011 time-frame. All are for specific customers of which the only announced one is TSMC.

      ASML calls these machines pre-production systems because they are too slow for volume production use. They can process 60 wafers an hour, whereas ASML’s 193nnm immersion scanner can process 140 wafers an hour.

      The other five customers which have booked pre-production EUV machines are almost certainly Samsung, Intel and IBM.”

      I would venture to guess that Toshiba/SanDisk is another of the unnamed pre-production EUV machine customers.

      Electronics Weekly goes on to say that: “ASML’s Phase 3, which is scheduled for 2013, will be for “high volume EUV systems running at very high speed,” an ASML spokesman told EW.”

      What “high volume” means exactly is another question.

      To my mind 2014, is probably a best case- for production 3D- EUV included.

      I agree EUV could be critical.


  8. savolainen says:

    Greetings bob779777,

    That question would be a good one to put to Eli directly. Maybe one of these days an analyst will give it a shot.

    At Investor Day Eli just said that accounting for all the complexity, it should come out cheaper:

    “Eli: 3D would require greater intensity of lithography because you are going say up to eight levels, you have the opportunity to generate 8 levels of memory and each level has a certain number of critical stages. So yes you would need more lithography and therefore the balance in that fab would be much more lithography and etch than furnaces lets say.

    But the idea is that after you account for all of this- you take all of this- more lithography- it still comes out cheaper per GB and hopefully it starts a new scaling path. It re-energizes Moore’s law.”


  9. woxberry says:

    Flip, Savo, and BOB,

    EUV could be sooner than we think

  10. AndyW says:

    Hi Savo,

    Will do once the article is published. As regards SanDisk getting 3-D Flash out on a product in 2014 – very possible. I think they are in the most advanced stage of all the big players especially with the Matrix acquisition. The problem they all face is that regular NAND Flash is at such an advanced level of sophistication while any 3-D technology has a lot of catching up to do. Therefore, it will be very interesting to see not only which 3-D technology will take over but also how this happens.

    All the best

  11. Chingadera says:

    Savo, Thanks for the kind wishes. Any idea what the “Something big” TBA on March 23rd could be? It is on Sandisks home page. Thanks. Chinga

    • savolainen says:

      Hey Chinga,

      I am inclined to think this will just a be 32 GB microSD. I see the “Something Big” as just a little teaser promo on the web site. I suppose it could be something more, but if so, I’d think SNDK would find a better way to telegraph the potential.


  12. sam says:

    Savo and anyone with 3D knowledge (AndyW),
    What do you guys think about Stan White and HP’s new gadget, memristors?

    White sounds like Stan Ovshinky to me–a brilliant dreamer. But HP isn’t ECD. On the other hand, Ovshinky managed to get Intel and other very large companies to give him hundreds of millions dollars to pursue his very creative dreams.

  13. AndyW says:

    My take on the HP memristor: it depends on resistance switching in a film of an oxide of titanium. This so-called “simple metal oxide” or SMO is part of a class of materials that is being studied by several companies. I know that Samsung has published in this area (Baek et al., IEDM 2005). Titanium oxide switching has a fairly long history with the first publication (as far as I know) back in 1968 (F. Argall in Solid-State Electronics). In a memory application, the switching material has to have a select device within a cell. Otherwise a unique cell could not be addressed. Sticking in such a select device (like a diode) is non-trivial. If you notice the HP picture of their memristor, they show one line perpendicular to many. This then gets around the need for an integrated select device for their prototype. However, to build a real memory they would need to make this step.

  14. hapa says:

    Sandisk 3D R/W seems to be working with all allotropes of carbon (resistor) – sp3, sp2, DLC, and even CNT. So nobody knows which one they’ll end up using. Their resistor element basically consists of alternate layers of carbon and doped-carbon patterned like zebra-crossing in 100nm length by 20nm, and maybe by 20nm. A diode, in series, is used as the current steering device. The dopant is used to make the cell workable in a practical voltage range.

    I would guess that their OTP antifuse cell is originally made of sp3 carbon that is programmed into sp2 (ie. from non-conducting to conducting state). So, if I’m correct, they’ve been tinkering with carbon based material for quite some time.

    I think cost/GB will be the overwhelming determinant for who will come out on top as far as memristor vs. PCM vs. Sandisk 3D R/W. I’ve seen a quote of ~ $60 to $70 currently for PCM.

    My questions are:
    1) For AndyW – Maybe I’m missing something, but how does your paper apply to Sandisk 3D R/W since there’s no charge trapping involves in the design?

    2)For Savo and all – Can Sandisk 3D R/W also be made into bit selectable? If it does, it has a far reaching application beyond the NAND flash. It probably won’t even need the ECC.

    Best regards.

  15. AndyW says:

    Hi hapa,

    The paper I referred to was in relation to BiCS and VRAT and how serious these are in relation to what SanDisk is doing. It was part of the BiCS discussion in the blog comment trail.

    All the best


    • savolainen says:

      Hey Andy and all,

      I am back now and catching up.

      These last few 3D-related comments are rather remarkable. Dense and informed.

      I really don’t have much to add. The game is afoot and a whole lot of $$$$ have placed their bets. We shall see in the next few years.

      As far as memristors go, conceptually they seem most attractive- as a whole lot of other technologies sound when a charismatic dreamer- to use Sam’s apt description- is waxing eloquently.

      Andy- thanks for your comments. How would you handicap HP’s memristors vs SNDK’s 3D R/W?

      My first take is context. SNDK lives and dies with memory, and therefore I give SNDK’s efforts and comments much more weight.


      • AndyW says:

        Welcome back Savo. HP’s memristors will need to incorporate a select device within each cell to be able to build a real memory. SanDisk’s acquisition of Matrix gave them the basic IP and technology for this plus they have such select devices in 3D write once products. So my take is that SanDisk is way ahead.

        All the best


  16. flip says:

    ASML’s timeline alone does not represent the readiness of EUV. The defect inspection for the reticles as well as the resist behavior, still have not been resolved. Even 2014-5 is too late for 1x nm. ASML is selling a double exposure tool already (nxt:1950i) – maybe that will be used with the self-aligned double patterning. Or maybe we can have some dual tone development.

    The 3D R/W is something interesting. A programmable silicon memory, so to speak. I wonder how much power it consumes. You need extra voltage across the diode, and the current through the semiconductor won’t be negligible either.

  17. sam says:

    Would like to get reactions from all on Macronix’s announcement. Here is Digitimes’ article on it:

    Macronix develops 3D NAND flash
    Josephine Lien, Taipei; Jessie Shen, DIGITIMES [Friday 25 June 2010]

    Macronix International has announced that its recent research results will pave the way for the company to develop scalable and efficient 3D NAND flash using its patented BE-SONOS (barrier engineering) charge-trapping technology and 3D decoding architecture.

    Macronix reported the fabrication and demonstration of an eight-layer, 75nm half-pitch, 3D VG (vertical gate) NAND flash using a junction-free BE-SONOS scheme in a paper presented at the 2010 Symposium on VLSI Technology earlier this month.

    “Traditional NAND flash will be facing technology barrier when it scales to below 2Xnm node” said CY Lu, president of Macronix. “The 3D memory cell array structure has been proposed to be the most promising candidate for NAND flash to shrink to below 1Xnm.”

    Using 3D stacking, NAND flash may achieve higher data storage capacity and effectively lower fabrication cost without relying on advances in lithography technology, according to Macronix. Several 3D NAND flash structures have been proposed, such as P-BiCS�]pipe-shaped bit cost scalable), TCAT�]terabit cell array transistor), VSAT (vertical stacked array transistor) and VG.

    Macronix said its work has chosen the VG architecture, believing it is the best approach. Simulation shows this structure could be scaled to 25nm node in a 3D array, providing density far beyond conventional 2D NAND Flash.

    Macronix expects products that adopt 3D NAND flash technology will be commercialized in 2014.

    Previous reports cited Macronix chairman Miin Wu as saying the company plans to deliver samples of its in-house developed NAND chips to potential customers in the first half of 2011, a milestone for Macronix’ entry into the NAND flash territory.

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