What a difference a year makes.
12 months ago, SanDisk was crashing and burning. Investor Day 2009 never took place. As Eli put it- it would have been like standing on the podium, as a Man-on-Fire, talking about how negative things looked.
The image below comes to mind.
Well that is then and this is now.
This year it was smiles all around. Even Judy delivered- with upped guidance for Q1- minutes after the market closed. Very clever too- to hold back on updating the full year til the Q1 conference call.
Keep ‘em guessing on how much up- up will be for 2010. Lots of headroom here.
SanDisk has the 5+ hour replay of Investor Day up for the listening. For any serious investor, this is great stuff. Carefully organized and served up on silver platter. Not to be missed.
As a follow-on to Investor Day, SanDisk participated in Morgan Stanley’s Tech Conference (MS) this last week- also available as a replay. Following close on the heels of Investor Day, it turned out to be an addendum of sorts with additional detail.
My plan is to work my way through this material carefully, over the next few months- as time allows- topic, by topic.
Today’s topic is SanDisk’s 3D Read/Write (R/W)- a huge looming story.
Heretofore SanDisk has been tight lipped. Those days now appear over. More info about 3D R/W was served up at this Investor’s Day and MS, than the previous 5 years of investor days, conference calls and conferences combined.
Why this change of heart- now?
I can think of several possible reasons- confidence that the technology is commercially viable; confidence that the core IP is secured; gamesmanship with competitors; and the calculated decision to start educating the investment community- before any fab 5 announcements.
Before getting into new stuff, a bit of background is probably in order.
SanDisk comes by its 3D chip technology through its acquisition of Matrix Semiconductor back in 2005. Probably $250 million very wisely spent.
Matrix itself was founded in 1998 by Thomas Lee of AMD/ Rambus; Mark Johnson of AMD/ Rambus/ MIPS/ Transmeta and Mike Farmwald, founder of Chromatic Research (and a co-founder of Rambus). Good bloodlines.
Matrix’s engineers adapted the normal manufacturing processes used for LCD screens to memory chips. They figured out how to layer polycrystalline silicon on top of a base chip and then re-crystallize it to form active 3D matrices.
Matrix’s 3D chip technology was something entirely different from NAND. It was not a variation of floating gate or charge trapping, but something referred to as antifuse.
Instead of storing electrical charges, the chip had gazillions of microscopic fuses. When info was read to such a chip, fuses were either blown or left alone, storing the info permanently (up to 100 years.)
Chips worked as advertised and shipped commercially.
So far so good, but the not-so minor problem was that this technology was only one-time programable (OTP). It stores data just fine, but only once. The chip was not re-programable.
The challenge Sandisk took up was to turn this OTP technology into read-write (R/W). Apparently great progress has been made.
Looking over the patent parade, SanDisk appears to have solved the R/W problem by setting resistance within the fuses- instead of just burning them away.
This breakthrough is accomplished by doping the semiconductor material forming the fuses. It even looks like it is possible to store multiple resistance states in the same memory cell- but no one is talking publicly about that.
Today SanDisk refers to its 3D (R/W) technology as scalable cross point diode arrays. SanDisk feels “3D R/W is the most likely successor for NAND in the coming decade.”
Memory Technologies’ Cost Curves
In this year’s Investor Day, Eli used the slide below to illustrate the potential story through 2016 and how various technologies might stack up in terms of cost per bit as far as their ability to disrupt NAND.
NAND as we know it, is slowing down as the technology runs up against physical limits. This is shown by the red NAND line flattening out in the black dotted section.
The slide shows the end of the road for NAND in 2014. This is likely just sloppy graphics. Eli made the point that (2D) NAND will likely be with us through 2020- though at the end likely serving legacy markets.
(SNDK) 3D is shown as starting up in 2013 in the optimistic scenario and 2014 in the conservative scenario. This same slide was shown in 2008 with 3D starting in 2012.
My guess is that fab 5 and 3D are tied together and when fab 5 was postponed, commercial 3D was too.
This slide also shows that Ferroelectric RAM, MRAM, and Phase Change Memory (PCM) don’t look competitive.
BICS is another matter. The optimistic BICS line and optimistic 3D line are shown one over the other.
When this same slide was shown in 2008, BICS was nowhere to be seen.
BICS is vertical NAND, being developed by Toshiba and also a variant is being developed by Samsung.
Toshiba calls its 3D NAND implementation: P-BiCS (Pipe-shaped Bit Cost Scalable) and in 2009 had a 16-layer, 32Gbit prototype chip, built using 60nm process technology.
3D BICS MLC is apparently enabled by the U-shaped cell string. According to press: only “One more breakthrough is required in the processes of stacking cells and opening the through-hole to lower the cost.”
This said, Toshiba had this technology back in 2008 when Toshiba decided to sign on with SanDisk to jointly develop SanDisk’s 3D cross point diode arrays. Toshiba also agreed to make licensing payments to SanDisk for the privilege.
The problem that BICS faces is the same problem that 2D NAND is facing: a declining numbers of electrons. SanDisk’s 3D resistive memory doesn’t depend on how many electrons are left.
On the other hand, BICS would seem to remain within the confines of the semiconductor industry maxim, being “change as little as possible”- a proven recipe for success.
BICS is one to watch.
SanDisk’s 3D (Read/Write) Memory- Scalable Cross-point Diode Array
At Investor’s Day Eli, commenting on this slide, noted that a 3D R/W chip with 8 layers of stacked cross-point diode arrays, which is equivalent to 8 bits per cell or 8x, is going to be feasible.
Eli also said that development is now proceeding at Yokkaichi, which likely means Fab 4.
This is new news. Then at MS, Eli elaborated that “it’s [3D] not in production. It’s not in pilot production. It’s in intensive R&D mode- very intensive.”
At Investor Day Eli went on to point out that SNDK 3D R/W, if successful, would trigger the second wave for SSDs:
“Now, if we are successful with 3D R/W, and by all means I say if, because until we do it, we haven’t done it. If we can succeed in that then 3D R/W would with the projected cost structure, will definitely give a second wave on the SSD.
Basically it has the economic [pause] you can kind of see it, if you take either the 3D optimistic or conservative, you can see that the cost, this is an exponential cost curve, is substantially lower than what can be done with NAND, and we also believe that issues like endurance will be far less, frankly, will not be an issue.”
Eli’s comment regarding endurance should be noted. BICS as a NAND variant would likely have the same endurance issues as 2D NAND.
If SanDisk 3D doesn’t have endurance issues and has best cost structure, then SNDK 3D SSDs (cross-point diode array technology) would look poised to displace hard disk drives across the board.
NAND and Post-NAND Fabs in the Coming Decade
Some of Eli’s comments on this slide from Investor Day on existing NAND fabs:
“ So what about this post-NAND? What’s going to happen to all those fabs? The existing NAND meg-fab is a very large fab- 200,000 wafer’s/month, 300mm. Will go to 1x nm.
By 2012/13, they will be highly depreciated. They will be highly cost effective. They will generate, I believe, very attractive margins for a long period of time. They will be throwing off a long tail, a long fat tail of cash, I believe, and very likely to the end of the decade.
And the reason for that is, because at 1x, you have such a good cost structure, particularly when you are depreciated. You can do 128Gbit chip and with that- 16GB on a chip- and with that you can cover a very very large train [??] of legacy products that are growing- the markets are growing.
So I think that these investments are going to have a second life, in fact benefit, from the fact that there is a slowdown in NAND and therefore there is far less need to continue to invest- to upgrade them. So basically you get to a certain point, you cannot go any further with immersion lithography, you are down at the edge. No one can do any better. And basically you have the market for that.”
In other words, for SanDisk/Toshiba Fabs 3 and 4 are going to end up as 1x NAND fabs based on immersion lithography. Eli took that thought and expanded it at MS:
“Eli Harari: Our assumption is that our existing captive supply for NAND will be gainfully employed at down to the 1x nanometer node for a long time to come and it would make very little sense for us to tear it up so we could get the clean room space to put any special equipment that’s required.
In the case and we’re talking about for 3D, the timing for 3D is such that we’re talking about really the advent of EUV lithography and that would require its own manufacturing space. It just makes no sense to take a very highly productive, highly depreciated NAND fab and stop it to three out of four [implies 75% of its life]. So 3D manufacturing would entail its own dedicated production.
Atif Malik: On that subject, there is quite a bit of debate about the timing of EUV the readiness of EUV. So I just want to get your thoughts on – we definitely need EUV at 11xnm or can we live with multiple patterning, triple or quadruple patterning to get it lower on its shrink path.
Eli: Right. So Intel has talked about going all the way to 11 nm with immersion scanners- through exposing a layer 5 times. You can do this when you only need to define one layer. For logic, for microprocessors, that may be possible- even though rather expensive.
But realistically for flash memory, NAND flash, or 3D, one of the most attractive features of EUV is that it takes you away from the need for multiple exposures. You don’t need to do dual exposure, double exposure, or 5x exposure- 5 times exposure.
Its single exposure, so even though the equipment may be more costly the throughput and productivity is better.
Now one of the things for us that 3D offers is at least in theory if we can make it work at 2x, technology node, we think that it should be much more readily scalable to 11 nm or whatever the lithography will allow us to do and therefore it will benefit to a greater degree from EUV than other technologies.”
Eli packed a lot into those brief comments. It appears that the plan is to produce commercial 3D at fab 5 at 1x using EUV. First 3D efforts will likely target 2x- probably in pilot production. Implied is that these efforts will be based on immersion lithography and likely in fab 4 when SanDisk/Toshiba gets to that node.
This post has gone on long enough, so I’m going to stop here.
Lots of ifs here with 3D. Lots of promise too.