NAND as we know it is reaching the end of the line. It’s been a good run.
But Judgement Day is Coming!
2014 looks like the year. Not so far off.
3D NAND looks like the technology ready to pick up where 2D NAND leaves off.
Post-NAND technologies like 3D resistive RAM, Ferroelectric RAM, MRAM, and Phase Change Memory (PCM) are not ready for prime time. This appears to leave the market with 3D NAND.
The thinking is that 3D NAND will be a replacement technology spanning between 2D planar NAND and whichever post-NAND technology emerges down the road. 3D NAND’s reign looks to be relatively short- lasting five to eight years.
3D NAND is true vertical NAND cell stacking not to be confused with chip stacking in a multi-chip package. In 3D NAND, NAND layers, not chips, are stacked in a single chip.
In many respects, 3D NAND is evolutionary, not revolutionary. The good news is continued cost reduction, smaller die sizes and more capacity. Also, installed NAND toolsets in the wafers fabs can, for the most part, be reused, thereby extending the useful life of fab equipment.
The bad news is that this 3D technology is still basically NAND with all its inherent limitations of data reliability and performance.
The wrinkle is that each of today’s NAND players has a different approach to 3D NAND.
Toshiba/SanDisk and Samsung are each developing variants of charge-trapped flash technology. Toshiba calls its 3D NAND: Pipe-shaped Bit-Cost Scalable or P-BICS.
Samsung dubs its 3D NAND: Terabit Cell Array Transistor or TCAT.
Hynix is pursuing a vertical floating-gate structure.
Micron hopes to transfer its DRAM expertise in deep trenches to 3D NAND.
In addition, Macronix is developing yet another 3D NAND charge-trapping technology based on its BE-SONOS technology.
This fragmentation is going to create winners, losers and chaos.
Winners
Its going to take deep pockets to hit the ground running. Samsung and Toshiba/SanDisk have the resources, as well as the expertise and mind-share with equipment suppliers to make a go of it.
They’ve also both had R&D engineering teams hammering away at the problem for a while now. Toshiba since 2007. Samsung apparently since soon thereafter.
Both TCAT and P-BICS are similar charge-trapped flash technologies with similar structures. Samsung and Toshiba have been engaging in a war of words since at least 2009 on which approach is superior.
SanDisk is late to the 3D NAND party, but looks positioned to ride Toshiba’s P-BICS coattails.
In April of this year in the Q1 SanDisk conference call, Sanjay announced that SanDisk would be joining forces forces with Toshiba to co-develop P-BICS.
Sanjay’s comments:
“In the first quarter, we made an incremental strategic technology investment with Toshiba that covers a variety of technologies including a three-dimensional NAND architecture, known as Bit Cost Scalable or BiCS, which Toshiba had been developing independently. We believe that SanDisk and Toshiba joining forces to co-develop BiCS will allow us to further build on our past decade of successful development of multiple generations of NAND flash technologies.
BiCS, if successfully developed and commercialized, can leverage the installed NAND toolsets in the wafers fabs very well, thereby extending the useful life of fab equipment. We expect BiCS to enable further memory cost reductions beyond the future 1Y or subsequent scaled NAND, until 3D Read/Write memory, which remains our ultimate goal, is fully ramped into high volume production.”
SanDisk’s incremental strategic technology investment with Toshiba in Q1 2011 was $115 million.
My guess is that SanDisk held off this long before backing 3D NAND because it believed that its 3D Read/Write memory based on scalable crosspoint diode arrays would be ready.
EUV technology appears to be critical for this post-NAND technology, and EUV is late.
Tick Tock.
Losers
Time will tell whether Macronix, Hynix, and Micron have what it takes for 3D NAND, but its going to be tough, especially if Samsung and Toshiba/SanDisk don’t stumble.
Today Samsung and Toshiba/SanDisk together account for about 75% of NAND production (by bits). Hynix and Micron/Intel together produce the remaining 25%.
Macronix isn’t even on the charts.
Samsung and Toshiba/SanDisk enjoy the economies of scale and R&D budgets that go with their market share.
If there’s a canary in this mine, that would be Micron’s NAND partner Intel.
While Micron has recently been talking up 3D NAND, there’s been nary a peep (that I’m aware of) from Intel.
This would be consistent with Intel’s retreat from the NAND business itself. Intel hasn’t contributed a dime towards the ramping joint Micron/Intel IMFS Singapore NAND fab in the last year or so. Micron on the other hand has had to pony up $1.565 billion.
This joint venture started off essentially 50/50. Today Micron’s ownership percentage is up to 86% (info from SEC filings).
A couple of years ago, Eli Harari summarized the challenges that the Micron/Intel (2D) NAND JVs faced- “It is tough to be number 4 in a rough neighborhood.”
It’s not going to get any easier with the arrival of 3D NAND and post-NAND technologies.
My guess is that Intel saw the writing on the wall, looked carefully at it’s options and contractual obligations, and has decided to tread water until a clean exit can be executed.
Clearly the world isn’t going to end as 2D NAND runs out of steam. The existing fabs even without 3D NAND are going to keep on chugging along throwing off a long tail of cash for years.
That said, the uncertainty of what’s coming next is going to loom. The whole NAND ecosystem is going to increasingly feel this pressure. Smaller players are particularly vulnerable. Especially, in an uncertain economy.
The Wall Street Journal noted last week that: “More than half of the U.S.-based companies making their domestic stock-market debuts this year are trading below their offer price, an ominous backdrop for any companies hoping to come public.”
Multi-billion dollar emerging markets are there for the taking. The technological roadmap is uncertain. Sounds like a recipe for chaos.
With chaos comes opportunity- especially for those like SanDisk positioned to emerge as winners. I’m going to stop here, and in my next post look at what SanDisk’s next move might be to complement the Pliant acquisition.
When the going gets tough, the tough go shopping.
SanDisk etc 
Hi Savo – Nice article explaining the vertical NANDs (BiCS and TCAT from Toshiba and Samsung respectively). These technologies are very attractive from the cost point of view if they can be made to work. One problem that both need to solve is the concept of the vanishing string current. This is the amount of current out of the vertical NAND string that needs to be detected and how it changes as the memory capacity (and therefore string length) increases. This is usually a closely-guarded secret but it turns out my company made devices that can be used to measure this and predict how it will behave with string length. The technical white paper is at:
Click to access Vanishing_String_Currents_White_Paper_2011.pdf
The key data is in Fig.8 on page 16 and in Table 1 on page 17.
The conclusion is quite clear – sub-nanoamp levels of string current can be expected in strings of length required for the products being spoken about using BiCS and TCAT.
Needless to say, the companies working on this problem have the best talent in the world. So if they can’t solve it, there is most likely no solution.
All the best
Andy W
Hi Andy,
Thanks once again for the info. And the link to your white paper(s).
I have shared your skepticism about 3D NAND, up until recently.
Now I’m guessing that real progress is being made. But I’m just guessing.
As you say the best talent in the world is working on the problem(s). There are mega-dollars and mega-markets there for the taking for the winners.
Mega-motivation.
I have two questions for you when you have the time.
Tell me if I’m wrong, but it strikes me that the vanishing string current problem might be an ongoing headache.
In other words, say it can be “solved” for 3D NAND at say 55nm, it would seem that the problem likely will need to be addressed once again, at the next node down. And then again on the next node beyond that.
Do you agree?
Secondly, in your mind is there a potential system approach that could help, or this simply a chip level problem?
In other words, how important potentially is the intelligence of the 3D NAND controller?
Thanks,
Savo
Hi Savo,
In answer to your first question, not only is it an ongoing headache but it only gets more painful for the following reason. The 3D NAND approaches (BiCS, pBICS and TCAT) all rely on placing the memory dielectric stack (the “ONO”) between NAND string columns. This ONO has to be of a certain thickness. This means that the minimum column diameter will be around 40nm – 50nm. Therefore, the only way to increase memory capacity on a single chip after reaching this column diameter is to lengthen the NAND string column. Therefore, increasing chip capacities mean vanishing string currents.
In answer to your second question, it remains to be seen whether any NAND system can detect sub-nA sense currents. Remember that this level is around a thousand times smaller than the current values being sensed now.
All the best
Andy
10Q:
“In the first quarter of fiscal year 2011, we made investments in Bit-Cost Scalable, or BiCS, and other technologies. We believe BiCS technology, if successful, could enable further memory cost reductions beyond the NAND roadmap, until, and if, 3D Read/Write technology is developed and fully ramped into high
volume production… we generate license and royalty revenues from NAND technology and we own intellectual property for 3D Read/Write and BiCS technology, and if NAND is
replaced by a technology other than 3D Read/Write or BiCS, our ability to generate license and royalty revenues would be reduced.”
10Q wording plus the way BICS is presented in the financials suggest that SanDisk purchased the IP rights from Toshiba and that now BICS status is similar to 3D R/W – SanDisk holds the IP and both companies join forces on the R&D front. Monetary, SanDisk invested $100M in purchasing the IP (the 115M once reported included 15M loan to Pliant), and it is spending heavily now on BICS R&D. I think that this large commitment by SanDisk indicate that SanDisk believes that it can overcome the technical problems and make BICS commercial by 2013.
Eli Harari – AD 2008
Slide 24 3D R/W Technology Options] On 3D R/W technology there are really three options that the industry is pursuing. The first one is stacked layers of NAND arrays on epitaxial silicon. This is a technology that Samsung is developing. They reported two layers of NAND on epi built on glass. I think the benefit of that is that it is NAND technology so it is familiar, but it is very difficult to build epitaxial layers outside of silicon and quite expensive.
Stacked layers of NAND arrays, not on epitaxial silicon, but on polysilicon, very much a technology that was first described by Matrix Semiconductor and in fact they have some of the basic patents on that. That is being pursued by several other companies including Toshiba which has a paper on that.
[ELI suggested that already Toshiba was building on Matrix patents and that SanDisk has extensive know-how on that approach. Perhaps 3D and BICS share many similar technical issues that both Toshiba and SanDisk felt that the right thing to do is to have same partnership structure as with 3D and to compensate Toshiba for past effort with $100M]
The third approach is stacked arrays of diodes, diode arrays. A diode is a two terminal device with either a fuse element or a switching element. This is what Matrix has done and what we have adopted since our acquisition of Matrix semiconductor.
SanDisk we believe has pretty fundamental patents, just about the major fundamental IP in 3D technology.
Hi Dan,
Thanks for pointing out the IP angle on BICS in SanDisk’s 10Q.
I agree with your read that SanDisk purchased IP rights from Toshiba, but I don’t necessarily think this means Toshiba gave up its rights.
In any case 3D NAND looks like it’s shaping up as an important storyline and I agree that SanDisk’s $100M investment indicates that it believes that the technical problems can be overcome.
IP for both 3D NAND and 3D R/W is going to be important. SanDisk appears to be well positioned thanks to the Matrix patents and the Toshiba relationship.
In the last couple of weeks I went back and looked through cc’s etc for Matrix IP commentary. I didn’t find anything better than you noted.
The key word seems to be “fundamental” in regards to 3D chip technology.
Regards,
Savo
Thanks, Savo. Read this last weekend but had to give it another read today.
“My guess is that SanDisk held off this long before backing 3D NAND because it believed that its 3D Read/Write memory based on scalable crosspoint diode arrays would be ready”
Is this to say/mean that the 3D technology from [SanDisk’s acquisition of Matrix Semiconductor] wasn’t viable and that SanDisk is leaving it behind to join Toshiba (on their technology)?
Hey Poofy,
Nah. My guess is that SanDisk is simply hedging its bets.
There are now three prongs to SanDisk’s chip strategy:
1. Continue scaling 2D planar NAND. Milk it for all the $$$ possible, as long as possible.
2. Work with Toshiba on 3D NAND (P-BICs). My guess is that it is going to work out eventually, but this not a sure thing.
3. Continue developing the 3D technology from Matrix.
The problem- at least as SanDisk explains it- is that EUV is required for the Matrix 3D R/W technology (scalable crosspoint diode arrays). And EUV is late. No one seems to really know when it will be ready for high volume production.
The ultimate goal is Matrix 3D R/W, but in the meantime, there is 3D NAND, which both Samsung and Toshiba are pushing on.
And until then, there is NAND as we know it (2D planar).
The good news is that the NAND producers are being prudent in their expansion planning. Which in turn means that all of them can make $$$.
Demand does not seem to be a problem.
My plan is to add more on 3D NAND in my next post. Hopefully next weekend.
There are several interesting angles I didn’t get to: What the equipment suppliers are seeing; IP; and acquisition potential as fallout from this chaos.
Best,
Savo
Thank you Professor Lainen for that great explanation of 3D NAND. I look forward to your thoughts on “There are several interesting angles I didn’t get to: What the equipment suppliers are seeing; IP; and acquisition potential as fallout from this chaos.”
Does Amazon’s Fire with 8GB storage foretell problems for us?
Hi gal2k,
Amazon’s Fire with 8GB storage should be a plus for several reasons. The Fire is probably the closest we’ve come to a cloud device so far.
The cloud should actually accelerate SSD adoption- Both in the cloud and in the devices optimized for the cloud.
All that content stored in the cloud has to be stored somewhere and delivered efficiently. SSDs are rapidly being adopted as the preferred solution.
Devices such as the Fire need to be light, thin and power-efficient, and hence use NAND.
True 8GB (and up) seems small. Drip, by drip, though, it adds up over millions of devices. This is all new demand.
And there is a good chance that there will be at least some SanDisk inside the Fire.
It looks likely that Amazon used Quanta for the Fire, the same designer/manufacturer as BlackBerry did for their Playbook tablet. According to the iFixit tear down, SanDisk iNAND is used in the Playbook.
The Fire teardown should be interesting.
Best,
Savo
Savo,
I have been reading your articles on SanDisk for the past five years now and appreciate your insights.
I was curious to see what your take is on the Micron earnings release for SanDisk.
Micron said that revs for NAND were up 11% year over year due to a 40% increase in sales volume partially offset by a decrease in average selling prices.
In my opinion, this probably bodes well for SanDisk in Q3 2011 and beyond due to SanDisk being a more efficient producer of NAND than Micron. This was evident in the stock price being up most of the day for SNDK until later when the market tanked. Still only finished down less than 1% and for the past month SNDK has recovered by 15%.
BARTSI
hi savo, thanks,
should samsung produce their version of 3D, what’s going to happen to royalties? is this still considered nand. it looks that if 3D isn’t considered regular nand, we might end paying royalties to toshiba or even to samsung.
thanks dan for a thorough review
How does Sandisk’s 3D fit with the 3D that they are discussing in the following EETimes article :
http://www.eetimes.com/electronics-news/4229474/Perfecting-the-3-D-chip
They mention a lot of companies, but not Sandisk or Toshiba. Eli always claimed that Matrix has fundamental patents for 3D, but I never see anyone else mention that fact. How come?
Hey Sam,
I really have no idea what Eli meant by fundamental. And he didn’t say fundamental, he said “pretty” fundamental. (joke)
I am inclined to translate “fundamental” in this context as potentially important, but probably not as significant as SanDisk’s flash patents.
Ultimately it will depend on what 3D post-NAND technology wins the day, what the keys are to its success, and when it actually goes into production (patent expiration).
There are lots of moving pieces right now.
Put another way, it’s probably most important for SanDisk to be one of the winners of the post-NAND technology race. And have the IP to back to it up.
While it might be nice to be able to collect license and royalty revenues as well, that might not be in the cards.
Personally, I’m not so sure the Matrix patents will be enough- but who knows.
The situation SanDisk doesn’t want to find itself in is Google’s current weak IP position in OSs.
Without strong enough in-house IP, Google is a sitting duck, for others looking to sink their Android efforts with the IP game. Google has the product in Android, but is scrambling without the IP- hence $12.5B for Motorola Mobility just to shore up it’s patent portfolio.
My guess is the Matrix patents are the sort of armor SanDisk will need when the going gets similarly tough in post-NAND.
FWIW, it’s starting to look to me like SanDisk’s 3D R/W will go the way of SanDisk’s SSD efforts. A wonderful early leading position (somewhat) squandered- but second chances delivered by slowly evolving technological and market forces.
Regards,
Savo
I think the 3-D that Sam referred to is so-called “heterogeneous” 3-D where chips that have been fabricated on different wafers are brought together vertically with die thinning and vertical interconnects using Through Silicon Vias (TSV). The 3-D NAND stuff we have been talking about is “monolithic” where each wafer starts in the fab and eventually comes out with multi-layers of memory on top through deposition and patterning and so on. The monolithic approach is always cheaper than the other approach and, if it can be done, will be the way for 3-D NAND, whatever 3-D NAND approach is eventually chosen. Examples of the monolithic approach are Matrix, BiCS, pBiCS, TCAT, Schiltron, VRAT, VSAT and so on. Heterogeneous 3-D is really for bringing together different chips that would be extremely difficult (and therefore highly costly if it were at all possible in the first place) to integrate such as DRAM, analog, high speed logic…..
I hope this helps.
Regards
Andy
Thanks Andy, that explanation helps me. I keep reading about TSVs, but have never heard SNDK mention them. So, the “hetero” approach implies stacking of NAND chips, whereas the “mono” approach suggests an end-to-end 3 dimensional design and fabrication process, right?
Exactly that MartyS.
All the best
Andy
Thanks for the clarification, Andy. Re-reading the EETimes article with your explanation in mind made it much more understandable.